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december 2004 copyright ? alliance semiconducto r. all rights reserved. ? 12/23/04, v 2.6 alliance semiconductor 1 of 19 3.3v 512k 32/36 pipelined burst synchronous sram AS7C33512PFS32A as7c33512pfs36a features ? organization: 524,288 words 32 or 36 bits ? fast clock speeds to 166 mhz ? fast clock to data access: 3.4/3.8 ns ?fast oe access time: 3.4/3.8 ns ? fully synchronous register-to-register operation ? single-cycle deselect ? asynchronous output enable control ? available in 100-pin tqfp package ? individual byte write and global write ? multiple chip enables for easy expansion ? 3.3v core power supply ? 2.5v or 3.3v i/o operation with separate v ddq ? linear or interleaved burst control ? snooze mode for reduced power-standby ? common data inputs and data outputs logic block diagram selection guide -166 -133 units minimum cycle time 6 7.5 ns maximum clock frequency 166 133 mhz maximum clock access time 3.4 3.8 ns maximum operating current 300 275 ma maximum standby current 90 80 ma maximum cmos standby current (dc) 60 60 ma q0 q1 512k 32/36 memory array burst logic clk clr ce address dq ce clk dq d clk dq byte write registers register dq c clk dq byte write registers dq b clk dq byte write registers dq a clk dq byte write registers enable clk dq register enable clk dq delay register ce output registers input registers power down dq[a:d] 4 36/32 19 17 19 19 gwe bwe bw d adv adsc adsp clk ce0 ce1 ce2 bw c bw b bw a oe zz lbo oe clk clk 36/32 36/32 a [18:0]
12/23/04, v 2.6 alliance semiconductor 2 of 19 AS7C33512PFS32A as7c33512pfs36a ? 16 mb synchronous sram products list 1,2 1 core power supply: vdd = 3.3v + 0.165v 2 i/o supply voltage: vddq = 3.3v + 0.165v for 3.3v i/o vddq = 2.5v + 0.125v for 2.5v i/o pl-scd : pipelined burst synchronous sram - single cycle deselect pl-dcd : pipelined burst synchronous sram - double cycle deselect ft : flow-through burst synchronous sram ntd 1 -pl : pipelined burst synchronous sram with ntd tm ntd-ft : flow-through burst synchronous sram with ntd tm org part number mode speed 1mx18 as7c331mpfs18a pl-scd 166/133 mhz 512kx32 AS7C33512PFS32A pl-scd 166/133 mhz 512kx36 as7c33512pfs36a pl-scd 166/133 mhz 1mx18 as7c331mpfd18a pl-dcd 166/133 mhz 512kx32 as7c33512pfd32a pl-dcd 166/133 mhz 512kx36 as7c33512pfd36a pl-dcd 166/133 mhz 1mx18 as7c331mft18a ft 7.5/8.5/10 ns 512kx32 as7c33512ft32a ft 7.5/8.5/10 ns 512kx36 as7c33512ft36a ft 7.5/8.5/10 ns 1mx18 as7c331mntd18a ntd-pl 166/133 mhz 512kx32 as7c33512ntd32a ntd-pl 166/133 mhz 512kx36 as7c33512ntd36a ntd-pl 166/133 mhz 1mx18 as7c331mntf18a ntd-ft 7.5/8.5/10 ns 512kx32 as7c33512ntf32a ntd-ft 7.5/8.5/10 ns 512kx36 as7c33512ntf36a ntd-ft 7.5/8.5/10 ns 1ntd: no turnaround delay. ntd tm is a trademark of alliance semiconductor corporation. all trademar ks mentioned in this docu ment are the property of their respective owners.
12/23/04, v 2.6 alliance semiconductor 3 of 19 AS7C33512PFS32A as7c33512pfs36a ? pin assignment 100-pin tqfp - top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 lbo a a a a a 1 a0 nc nc v ss v dd a a a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 bwd bwc bwb bwa ce2 v dd v ss clk gwe bwe oe adsc adsp adv a a tqfp 14 x 20mm a nc/dqpc dqc0 dqc1 v ddq v ssq dqc2 dqc3 dqc4 dqc5 v ssq v ddq dqc6 dqc7 nc v dd nc v ss dqd0 dqd1 v ddq v ssq dqd2 dqd3 dqd4 dqd5 v ssq v ddq dqd6 dqd7 nc/dqpd dqpb/nc dqb7 dqb6 v ddq v ssq dqb5 dqb4 dqb3 dqb2 v ssq v ddq dqb1 dqb0 v ss zz dqa7 dqa6 v ddq v ssq dqa5 dqa4 dqa3 dqa2 v ssq v ddq dqa1 dqa0 dqpa/nc v dd nc note: for pins 1, 30, 51, and 80, nc applies to the x32 configuration. dqpn appl ies to the x36 configuration.
? AS7C33512PFS32A as7c33512pfs36a 12/23/04, v 2.6 alliance semiconductor 4 of 19 functional description the AS7C33512PFS32A/36a is a high-perform ance cmos 16-mbit synchronous static random access memory (sram) device organized as 524,288 words x 32/36. it incor porates a two-stage register-register pipe line for highest frequency on any given t echnology. fast cycle times of 6/7.5 ns with clock access times (t cd ) of 3.4/3.8 ns enable 166, and 133 mhz bus frequencies. three chip enable (ce ) inputs permit easy memory expa nsion. burst operation is initia ted in one of two ways: the c ontroller address strobe (adsc ), or the processor address strobe (adsp ). the burst advance pin (adv ) allows subsequent interna lly generated burst addresses. read cycles are initiated with adsp (regardless of we and adsc ) using the new external address clocked into the on-chip address register when adsp is sampled low, the chip enables are sampled active, and the output buffer is enabled with oe . in a read operation, the data accessed by the current address re gistered in the address registers by the positiv e edge of clk are carried to the data-out reg isters and driven on the output pins on the next positive edge of clk. adv is ignored on the clock edge that samples adsp asserted, but is sampled on all subsequent clock edges. address is incremented internally for the next access of the burst when adv is sampled low and both address strobes are high. burst mode is selectable with the lbo input. with lbo unconnected or driven high, burst operations use an interleaved count sequence. with lbo driven low, the device us es a linear count sequence. write cycles are performed by disa bling the output buffers with oe and asserting a write comma nd. a global write enable gwe writes all 32/ 36 regardless of the stat e of individual bw[a:d] inputs. alternately, when gwe is high, one or more bytes may be written by asserting bwe and the appropriate individual byte bwn signals. bwn is ignored on the clock edge that samples adsp low, but it is sampled on all subsequent cl ock edges. output buffers are disabled when bwn is sampled low regardless of oe . data is clocked into the da ta input register when bwn is sampled low. address is incremented internally to the next burst address if bwn and adv are sampled low. this device operates in single-cycle deselect feature during read cycles. read or write cycles may also be initiated with adsc instead of adsp . the differences between cycles initiated with adsc and adsp are as follows: ?adsp must be sampled high when adsc is sampled low to initiate a cycle with adsc . ?we signals are sampled on the clock edge that samples adsc low (and adsp high). ? master chip enable ce0 blocks adsp , but not adsc . the AS7C33512PFS32A/36a family operates from a core 3.3v power supply. i/os use a separa te power supply that can operate at 2.5 v or 3.3v. these devices are availabl e in a 100-pin tqfp package. tqfp capacitance * guaranteed not tested tqfp thermal resistance parameter symbol test conditions min max unit input capacitance c in * v in = 0v - 5 pf i/o capacitance c i/o * v out = 0v - 7 pf description conditions symbol typical units thermal resistance (junction to ambient) 1 1 this parameter is sampled test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 1?layer ja 40 c/w 4?layer ja 22 c/w thermal resistance (junction to top of case) 1 jc 8 c/w
12/23/04, v 2.6 alliance semiconductor 5 of 19 AS7C33512PFS32A as7c33512pfs36a ? signal descriptions snooze mode snooze mode is a low current, power-dow n mode in which the device is dese lected and current is reduced to i sb2 . the duration of snooze mode is dictated by the lengt h of time the zz is in a high state. the zz pin is an asynchronous, active high input that causes the device to enter snooze mode. when the zz pin becomes a logic high, i sb2 is guaranteed after the time t zzi is met. after entering snooze mode, all inputs except zz is disabled and all outputs go to high-z. any operation pending when entering snooze mode is not gua ranteed to successfully comple te. therefore, snooze mode (read or write) must not be initiated until valid pending opera tions are completed. similarly, when exit ing snooze mode during t pus , only a deselect or read cycle should be given while the sram is transitioning out of snooze mode. pin i/o properties description clk i clock clock. all inputs except oe , zz, and lbo are synchronous to this clock. a,a0,a1 i sync address. sampled when all chip enables are active and when adsc or adsp are asserted. dq[a,b,c,d] i/o sync data. driven as output when the chip is enabled and when oe is active. ce0 isync master chip enable. sample d on clock edges when adsp or adsc is active. when ce0 is inactive, adsp is blocked. refer to the ?synchronous truth table? for more information. ce1, ce2 isync synchronous chip enables, active high, and active low, respective ly. sampled on clock edges when adsc is active or when ce0 and adsp are active. adsp i sync address strobe processor. asserted low to load a new address or to enter standby mode. adsc i sync address strobe controller. asserted low to load a new address or to enter standby mode. adv i sync advance. asserted low to continue burst read/write. gwe isync global write enable. assert ed low to write all 32/36 an d 18 bits. when high, bwe and bw[a:d] control write enable. bwe i sync byte write enable. asserted low with gwe high to enable effect of bw[a:d] inputs. bw[a,b,c,d] isync write enables. used to control wr ite of individual bytes when gwe is high and bwe is low. if any of bw[a:d] is active with gwe high and bwe low, the cycle is a write cycle. if all bw[a:d] are inactive, the cycle is a read cycle. oe i async asynchronous output enable. i/o pins are driven when oe is active and chip is in read mode. lbo istatic selects burst mode. when tied to v dd or left floating, device follow s interleaved burst order. when driven low, device follows linear burst order. this signal is internally pulled high. zz i async snooze. places device in low power mode ; data is retained. connect to gnd if unused. nc - - no connect
? AS7C33512PFS32A as7c33512pfs36a 12/23/04, v 2.6 alliance semiconductor 6 of 19 write enable truth table (per byte) key: x = don?t care, l = low, h = high, n = a, b, c, d; bwe , bwn = internal write signal. asynchronous truth table notes: 1. x means ?don?t care? 2. zz pin is pulled down internally 3. for write cycles that follows read cycles, the output buffers must be disabled with oe , otherwise data bus contention will occur. 4. snooze mode means power down state of which st and-by current does not depend on cycle times 5. deselected means power down state of whic h stand-by current depends on cycle times burst sequence table function gwe bwe bwa bwb bwc bwd write all bytes lxxxxx hlllll write byte a hllhhh write byte c and d hlhhll read hhxxxx hlhhhh operation zz oe i/o status snooze mode h x high-z read l l dout l h high-z write l x din, high-z deselected l x high-z interleaved burst address (lbo = 1) linear burst address (lbo = 0) a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 starting address 0 0 0 1 1 0 1 1 starting address 0 0 0 1 1 0 1 1 first increment 0 1 0 0 1 1 1 0 first increment 0 1 1 0 1 1 0 0 second increment 1 0 1 1 0 0 0 1 second increment 1 0 1 1 0 0 0 1 third increment 1 1 1 0 0 1 0 0 third increment 1 1 1 0 0 1 1 0
12/23/04, v 2.6 alliance semiconductor 7 of 19 AS7C33512PFS32A as7c33512pfs36a ? synchronous truth table [4] ce0 1 1 x = don?t care, l = low, h = high ce1 ce2 adsp adsc adv write [2] 2 for write , l means any one or more by te write enable signals (bwa , bwb , bwc or bwd ) and bwe are low or gwe is low. write = high for all bwx , bwe , gwe high. see "write enable truth table (per byte)," on page 6 for more information. oe address accessed clk operation dq hxxxlx x x na l to h deselecthi ? z l l x l x x x x na l to h deselect hi ? z l l x h l x x x na l to h deselect hi ? z l x h l x x x x na l to h deselect hi ? z l x h h l x x x na l to h deselect hi ? z l h l l x x x l external l to h begin read q l h l l x x x h external l to h begin read hi ? z l h l h l x h l external l to h begin read q l h l h l x h h external l to h begin read hi ? z xxxhhl h l next l to hcontinue readq xxxhhl h h next l to hcontinue readhi ? z xxxhhh h l current l to hsuspend readq xxxhhh h h current l to hsuspend readhi ? z hxxxhl h l next l to hcontinue readq hxxxhl h h next l to hcontinue readhi ? z hxxxhh h l current l to hsuspend readq hxxxhh h h current l to hsuspend readhi ? z l h l h l x l x external l to h begin write d 3 3 for write operation following a read, oe must be high before the input data set up time and held high throughout the input hold time 4 zz pin is always low. xxxhhl l x next l to hcontinue writed hxxxhl l x next l to hcontinue writed xxxhhh l x current l to hsuspend writed hxxxhh l x current l to hsuspend writed
? AS7C33512PFS32A as7c33512pfs36a 12/23/04, v 2.6 alliance semiconductor 8 of 19 absolute maximum ratings stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any ot her conditions outside those indicated in th e operational sections of this specificat ion is not implied. exposure to abso- lute maximum rating conditions may affect reliability. recommended operating conditions at 3.3v i/o recommended operating conditions at 2.5v i/o parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.5 +4.6 v input voltage relative to gnd (input pins) v in ?0.5 v dd + 0.5 v input voltage relative to gnd (i/o pins) v in ?0.5 v ddq + 0.5 v power dissipation p d ?1.8w short circuit output current i out ? 20 ma storage temperature t stg ?65 +150 o c temperature under bias t bias ?65 +135 o c parameter symbol min nominal max unit supply voltage for inputs v dd 3.135 3.3 3.465 v supply voltage for i/o v ddq 3.135 3.3 3.465 v ground supply vss 0 0 0 v parameter symbol min nominal max unit supply voltage for inputs v dd 3.135 3.3 3.465 v supply voltage for i/o v ddq 2.375 2.5 2.625 v ground supply vss 0 0 0 v
12/23/04, v 2.6 alliance semiconductor 9 of 19 AS7C33512PFS32A as7c33512pfs36a ? dc electrical characteristics for 3.3v i/o operation dc electrical characteristics for 2.5v i/o operation ? lbo and zz pins have an internal pull-u p or pull-down, and input leakage = 10 a. * v ih max < vdd +1.5v for pulse width less than 0.2 x t cyc ** v il min = -1.5 for pulse width less than 0.2 x t cyc i dd operating conditions and maximum limits parameter sym conditions min max unit input leakage current ? |i li |v dd = max, 0v < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, 0v < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 2* v dd +0.3 v i/o pins 2* v ddq +0.3 input low (logic 0) voltage v il address and control pins -0.3** 0.8 v i/o pins -0.5** 0.8 output high voltage v oh i oh = ?4 ma, v ddq = 3.135v 2.4 ? v output low voltage v ol i ol = 8 ma, v ddq = 3.465v ? 0.4 v parameter sym conditions min max unit input leakage current ? |i li |v dd = max, 0v < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, 0v < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 1.7* v dd +0.3 v i/o pins 1.7* v ddq +0.3 v input low (logic 0) voltage v il address and control pins -0.3** 0.7 v i/o pins -0.3** 0.7 v output high voltage v oh i oh = ?4 ma, v ddq = 2.375v 1.7 ? v output low voltage v ol i ol = 8 ma, v ddq = 2.625v ? 0.7 v parameter sym conditions -166 -133 unit operating power supply current 1 1 i cc given with no output loading. i cc increases with faster cycle times and greater output loading. i cc ce0 < v il , ce1 > v ih , ce2 < v il , f = f max , i out = 0 ma, zz < v il 300 275 ma standby power supply current i sb all v in 0.2v or > v dd ? 0.2v, deselected, f = f max , zz < v il 90 80 ma i sb1 deselected, f = 0, zz < 0.2v, all v in 0.2v or v dd ? 0.2v 60 60 i sb2 deselected, f = f max , zz v dd ? 0.2v, all v in v il or v ih 50 50
? AS7C33512PFS32A as7c33512pfs36a 12/23/04, v 2.6 alliance semiconductor 10 of 19 timing characteristics over operating range snooze mode electrical characteristics parameter sym ?166 ?133 unit notes 1 1 see ?notes? on page 16. min max min max clock frequency f max ? 166 ? 133 mhz cycle time t cyc 6 ? 7.5 ? ns clock access time t cd ?3.4?3.8ns output enable low to data valid t oe ?3.4?3.8ns clock high to output low z t lzc 0?0?ns2,3,4 data output invalid from clock high t oh 1.5?1.5? ns 2 output enable low to output low z t lzoe 0?0?ns2,3,4 output enable high to output high z t hzoe ? 3.4 ? 3.8 ns 2,3,4 clock high to output high z t hzc ? 3.4 ? 3.8 ns 2,3,4 output enable high to invalid output t ohoe 0?0?ns clock high pulse width t ch 2.4?2.4? ns 5 clock low pulse width t cl 2.3?2.4? ns 5 address setup to clock high t as 1.5?1.5? ns 6 data setup to clock high t ds 1.5?1.5? ns 6 write setup to clock high t ws 1.5 ? 1.5 ? ns 6,7 chip select setup to clock high t css 1.5 ? 1.5 ? ns 6,8 address hold from clock high t ah 0.5?0.5? ns 6 data hold from clock high t dh 0.5?0.5? ns 6 write hold from clock high t wh 0.5 ? 0.5 ? ns 6,7 chip select hold from clock high t csh 0.5 ? 0.5 ? ns 6,8 adv setup to clock high t advs 1.5?1.5? ns 6 adsp setup to clock high t adsps 1.5?1.5? ns 6 adsc setup to clock high t adscs 1.5?1.5? ns 6 adv hold from clock high t advh 0.5?0.5? ns 6 adsp hold from clock high t adsph 0.5?0.5? ns 6 adsc hold from clock high t adsch 0.5?0.5? ns 6 description conditions symbol min max units current during snooze mode zz > v ih i sb2 50 ma zz active to input ignored t pds 2cycle zz inactive to input sampled t pus 2cycle zz active to snooze current t zzi 2cycle zz inactive to exit snooze current t rzzi 0cycle
12/23/04, v 2.6 alliance semiconductor 11 of 19 AS7C33512PFS32A as7c33512pfs36a ? key to switching waveforms timing waveform of read cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. bw[a:d] is don?t care. don?t care falling input rising input undefined ce1 t cyc t ch t cl t adsps t adsph t as t ah t ws t advs t oh clk adsp adsc address gwe , bwe ce0 , ce2 adv oe dout t css t hzc t cd t wh t advh t hzoe t adscs t adsch load new address adv inserts wait states q(a2y10) q(a2y11) q(a3) q(a2) q(a2y01) q(a3y01) q(a3y10) q(a1) a2 a1 a3 t oe t lzoe t csh read q(a1) suspend read q(a1) read q(a2) burst read q(a 2y01 ) read q(a3) dsel burst read q(a 2y10 ) suspend read q(a 2y10 ) burst read q(a 2y11 ) burst read q(a 3y01 ) burst read q(a 3y10 ) burst read q(a 3y11 )
? AS7C33512PFS32A as7c33512pfs36a 12/23/04, v 2.6 alliance semiconductor 12 of 19 timing waveform of write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t cyc t cl t adsps t adsph t adscs t adsch t as t ah t ws t wh t css t advs t ds t dh clk adsp adsc address bwe ce0 , ce2 adv oe din t csh t advh d(a2y01) d(a2y10) d(a3) d(a2) d(a2y01) d(a3y01) d(a3y10) d(a1) d(a2y11) adv suspends burst adsc loads new address a1 a2 a3 t ch ce1 bw[a:d] read q(a1) sus- pend write d(a1) read q(a2) suspend write d(a 2 ) adv burst write d(a 2y01 ) suspend write d(a 2y01 ) adv burst write d(a 2y10 ) write d(a 3 ) burst write d(a 3y01 ) adv burst write d(a 2y11 ) adv burst write d(a 3y10 )
12/23/04, v 2.6 alliance semiconductor 13 of 19 AS7C33512PFS32A as7c33512pfs36a ? timing waveform of read/write cycle (adsp controlled; adsc high) note: y = xor when lbo = high/no connect; y = add when lbo = low. t ch t cyc t cl t adsps t adsph t as t ah t ws t wh t advs t ds t dh t oh clk adsp address gwe ce0 , ce2 adv oe din dout t cd t advh t lzoe t oe t lzc q(a1) q(a3y01) d(a2) q(a3) q(a3y10) q(a3y11) a1 a2 a3 ce1 t hzoe dsel suspend read q(a1) read q(a1) suspend write d(a 2 ) adv burst read q(a 3y01 ) adv burst read q(a 3y10 ) adv burst read q(a 3y11 ) read q(a2) read q(a3)
12/23/04, v 2.6 alliance semiconductor 14 of 19 AS7C33512PFS32A as7c33512pfs36a ? timing waveform of read/write cycle(adsc controlled, adsp = high) t cyc t ch t cl t adsch clk adsc address a2 a1 t adscs a3 a4 a6 a5 a7 a8 a9 t ah t as gwe t wh t ws t csh ce0 ,ce2 t css adv t lzoe t oe t hzoe q(a1) q(a2) q(a3) q(a4) q(a8) q(a9) t lzoe t oh d(a6) d(a7) d(a5) t ds t dh oe dout din read q(a1) read q(a2) read q(a3) read q(a4) write d(a5) write d(a6) write d(a7) read q(a8) read q(a9) ce1
12/23/04, v 2.6 alliance semiconductor 15 of 19 AS7C33512PFS32A as7c33512pfs36a ? timing waveform of power down cycle t cyc t ch t cl t adsps clk adsp address a1 t adsps a2 gwe t wh t ws t csh ce0 ,ce2 t css adv t lzoe t oe t hzoe q(a1) d(a2( y 01)) d(a2) oe dout din adsc t hzc t pds zz setup cycle t pus zz recovery cycle n ormal operation mode ce1 zz read q(a1) s uspend read q(a1) c on - tinue write d(a2 y 01) s uspend write d(a2) read q(a2) sleep i sb2 state t zzi t rzzi i supply
? AS7C33512PFS32A as7c33512pfs36a 12/23/04, v 2.6 alliance semiconductor 16 of 19 ac test conditions notes 1 for test conditions, see ?ac test conditions?, figures a, b, and c. 2 this parameter is measured with output load condition in figure c. 3 this parameter is sample d but not 100% tested. 4t hzoe is less than t lzoe , and t hzc is less than t lzc at any given temperature and voltage. 5t ch is measured as high if above vih, and t cl is measured as low if below vil. 6 this is a synchronous device. all addresses must meet the specified setup and hold tim es for all rising edges of clk. all othe r synchronous inputs must meet the setup and hold times for all rising edges of cl k when chip is enabled. 7 write refers to gwe , bwe , and bw[a:d] . 8 chip select refers to ce0 , ce1 , and ce2 . z 0 = 50 ? d out 50 ? figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v ? output load: for t lzc , t lzoe , t hzoe , t hzc , see figure c. for all others, see figure b. ? input pulse level: gnd to 3v. see figure a. ? input rise and fall time (measured at 0.3v an d 2.7v): 2 ns. see figure a. ? input and output timing reference levels: 1.5v. v l = 1.5v for 3.3v i/o; = v ddq /2 for 2.5v i/o thevenin equivalent: 353 ?/1538? 5 pf* 319 ?/1667? d out gnd figure c: output load(b) *including scope and jig capacitance +3.3v for 3.3v i/o; /+2.5v for 2.5v i/o
12/23/04, v 2.6 alliance semiconductor 17 of 19 AS7C33512PFS32A as7c33512pfs36a ? package dimensions 100-pi n quad flat pack (tqfp) tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.85 16.15 he 21.80 22.20 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters a1 a2 l1 l c he e hd d b e
? AS7C33512PFS32A as7c33512pfs36a 12/23/04, v 2.6 alliance semiconductor 18 of 19 ordering information note: add suffix ?n? to the above part number for lead free parts (ex. AS7C33512PFS32A-166tqcn) part numbering guide 1.alliance semic onductor sram prefix 2.operating voltage: 33 = 3.3v 3.organization: 512 = 512k 4.pipelined mode 5.deselect: s = single cycle deselect 6.organization: 32 = x 32; 36 = x 36 7.production version: a = first production version 8.clock speed (mhz) 9.package type: tq = tqfp 10.operating temperature: c = commercial ( 0 c to 70 c); i = industrial ( -40 c to 85 c) 11. n = lead free part package & width 166 mhz 133 mhz tqfp x32 AS7C33512PFS32A-166tqc AS7C33512PFS32A-133tqc AS7C33512PFS32A-166tqi AS7C33512PFS32A-133tqi tqfp x36 as7c33512pfs36a-166tqc as7c33512pfs36a-133tqc as7c33512pfs36a-166tqi as7c33512pfs36a-133tqi as7c 33 512 pf s 32/36 a ?xxx tq c/i x 1234567891011
? AS7C33512PFS32A as7c33512pfs36a alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number: AS7C33512PFS32A-36a document version: v 2.6 ? copyright 2003 alliance semic onductor corporation. all rights reserved. our th ree-point logo, our name and intelliwatt are tr ademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsib ility for any errors that may appear in this document. the da ta contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the inform ation in this product data sheet is intended t o be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or custome r. alliance does not assume any responsibility or liability arising out of the applicatio n or use of any product described herein, and disclaims any expr ess or implied warran ties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantab ility, or infringement of any intellectual property ri ghts, except as express agreed to in alliance's terms and conditions of sale (which ar e available from alliance). all sales of alliance products are ma de exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; m ask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alli ance does not authorize its products for use as critical compone nts in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to th e user, and the inclusion of alliance products in su ch life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. ?

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